Currently, advanced power management (APM) and advanced configuration and power interface (ACPI) are the main power management systems in computer systems. In APM, the power management is controlled by Basic Input/Output System (BIOS) and APM is a power management system with low efficiency for early stage. However, in ACPI, the power management is controlled by Operating System (OS). There are four states of ACPI power management in a computer system and they are Global (G) state, Device (D) state, Sleeping (S) state and central processor unit (CPU, C) state.
Referring to FIG. 1, a schematic diagram illustrating a conventional CPU (C) operates under ACPI power management is showed. In FIG. 1, a CPU can work under four power states: C0 state, C1 state, C2 state and C3 state. While in the C0 state, the CPU works to execute instructions normally. While in the C1 state, The CPU is in halt mode, but still maintains cache integrity. While in the C2 state, the power savings of the C1 state are improved and specifically for multiprocessor systems such that one CPU is in halt mode and the others continue operation. While in the C3 state, the power savings of the C1 and C2 state are improved and the CPU is effectively switched off. Under C1, C2 and C3 states, an OS allows the CPU to enter a proper low power state based on the status of the CPU in order to achieve power savings.
The C3 state offers improved power savings over the C1 and C2 states. Before the CPU enters the C3 state, a command is sent by the OS to disable arbiters of a South Bridge and a North Bridge. Moreover, the events for processing aren't transmitted from the South Bridge or the North Bridge to the CPU in the C3 state until the CPU returns to the C0 state. After the arbiters of the South Bridge and the North Bridge are both disabled, the CPU enters the C3 state immediately. While in the C3 state, the CPU's caches maintain state but the CPU is not required to snoop bus master or CPU accesses to memory.
As can be seen from FIG. 1, the CPU begins work in the C0 state, which is a normal operation state, and then enters the C1, C2 or C3 state, which means the power savings state. If an interrupt request signal or a bus master signal is issued for dealing with, the CPU will return to the C0 state whether it is in the C1, C2 or C3 state. However, the power savings performance of the recovery mechanism is not good enough, in particular that it is extremely worse when the CPU is originally in the C3 state. While the arbiters of the North Bridge and the South Bridge are enabled only for transmitting data between those peripheral devices of the North Bridge or the South Bridge and a memory in a computer system, a bus master signal is issued from the peripheral devices and the CPU immediately returns to the C0 state from the C3 state. And then, the bus master signal can be transmitted to the CPU via the arbiters for snooping in order to transmit data between the peripheral devices and the memory in the computer system. However, under the above conditions, snooping the bus master signal, the CPU keeps staying in the C2 state without returning to the C0 state with extra power consumption.
Therefore, a method for a power management of a CPU is provided to overcome the above problems. If the North Bridge or the South Bridge receives a bus master signal, the CPU is allowable to enter a low power state allowing snooping from a low power state without snooping and the bus master signal can be snooped.